This invention relates generally to the isolation of tightly packed elements in semiconductor structures, and, more specifically, to the electric field isolation of neighboring charge storage elements of non-volatile flash electrically erasable and programmable read-only-memory (flash EEPROM) cell arrays.
In a first category of flash memory array architectures, memory cells are connected between adjacent bit line source and drain diffusions that extend in a column direction with control gates connected to word lines extending along rows of cells. One common memory cell has a “split-channel” between source and drain diffusions. A charge storage element of the cell is positioned over one portion of the channel and the word line (also referred to as a control gate) is positioned over the other channel portion as well as over the charge storage element. This effectively forms a cell with two transistors in series, one (the memory transistor) with a combination of the amount of charge on the charge storage element and the voltage on the word line controlling the amount of current that can flow through its portion of the channel, and the other (the select transistor) having the word line alone serving as its gate. The word line extends over a row of charge storage elements. Examples of such cells, their uses in memory systems and methods of manufacturing them are given in U.S. Pat. Nos. 5,070,032, 5,095,344, 5,315,541, 5,343,063, 5,661,053, and 6,281,075.
A modification of this split-channel flash EEPROM cell adds a steering gate positioned between the charge storage element and the word line. Each steering gate of an array extends over one column of charge storage elements, perpendicular to the word line. The effect is to relieve the word line from having to perform two functions at the same time when reading or programming a selected cell. Those two functions are (1) to serve as a gate of a select transistor, thus requiring a proper voltage to turn the select transistor on and off, and (2) to drive the voltage of the charge storage element to a desired level through an electric field (capacitive) coupling between the word line and the charge storage element. It is often difficult to perform both of these functions in an optimum manner with a single voltage. With the addition of the steering gate, the word line need only perform function (1), while the added steering gate performs function (2). The use of steering gates in a flash EEPROM array is described, for example, in U.S. Pat. Nos. 5,313,421 and 6,222,762.
Another type of memory array in this category that has been used commercially for many years uses an ETOX™ cell attributed to Intel Corporation. Individual memory cells are connected between a common source and shared drain lines. An early article describing this type of memory cell and array by Kynett V. N., Baker A., Fandrich M., Hoekstra G., Jungroth O., Kreifels J. and Wells S. is titled “An In-system Reprogrammable 256 K CMOS Flash Memory”, ISSCC Conf. Proc., (1988) p. 132.
In a second category of flash memory array architectures, generally referred to as NAND arrays, series strings of more than two memory cells, such as 16 or 32, are connected along with one or more select transistors between individual bit lines and a reference potential to form columns of cells. Word lines extend across cells within a large number of these columns. An individual cell within a column is read and verified during programming by causing the remaining cells in the string to be turned on hard so that the current flowing through a string is dependent upon the level of charge stored in the addressed cell. An example of a NAND architecture array and its operation as part of a memory system is found in U.S. Pat. Nos. 5,570,315, 5,774,397 and 6,046,935.
Increasing Data Storage Density
As in most all integrated circuit applications, the pressure to shrink the silicon substrate area required to implement some integrated circuit function also exists with flash EEPROM arrays. It is continually desired to increase the amount of digital data that can be stored in a given area of a silicon substrate, in order to increase the storage capacity of a given size memory card and other types of packages, or to both increase capacity and decrease size. One way to increase the storage density of data is to store more than one bit of data per memory cell. This is accomplished by defining more than two threshold levels as storage states for each storage element transistor, four such states (2 bits of data per storage element) now being included in commercial products. More storage states, such as 8 states (3 data bits) and 16 states (4 data bits) per storage element, are contemplated. Each storage element memory transistor has a certain total range (window) of threshold voltages in which it may practically be operated, and that range is divided into the number of states defined for it plus margins between the states to allow for them to be clearly differentiated from one another. A multiple state flash EEPROM structure and operation is described in U.S. Pat. Nos. 5,043,940 and 5,172,338, for example.
Another type of memory cell includes two storage elements that may also be operated in multiple states on each storage element. In this type of cell, two storage elements are included over its channel between source and drain diffusions with a select transistor in between them. A steering gate is included along each column of storage elements and a word line is provided thereover along each row of storage elements. When accessing a given storage element for reading or programming, the steering gate over the other storage element of the cell containing the storage element of interest is raised sufficiently high to turn on the channel under the other storage element no matter what charge level exists on it. This effectively eliminates the other storage element as a factor in reading or programming the storage element of interest in the same memory cell. For example, the amount of current flowing through the cell, which can be used to read its state, is then a function of the amount of charge on the storage element of interest but not of the other storage element in the same cell. Examples of this cell array architecture and operating techniques are described in U.S. Pat. Nos. 5,712,180, 6,103,573 and 6,151,248.
Charge Storage Elements
The charge storage elements of current flash EEPROM arrays and discussed in the foregoing referenced patents and articles are most commonly electrically conductive floating gates, typically formed from doped polysilicon material. Another type of memory cell useful in flash EEPROM systems utilizes a non-conductive dielectric material in place of a conductive floating gate to store charge in a non-volatile manner. Such a cell is described in an article by Chan et al., “A True Single-Transistor Oxide-Nitride-Oxide EEPROM Device,” IEEE Electron Device Letters, Vol. EDL-8, No. 3, March 1987, pp. 93-95. A triple layer dielectric formed of silicon oxide, silicon nitride and silicon oxide (“ONO”) is sandwiched between a conductive control gate and a surface of a semi-conductive substrate above the memory cell channel. The cell is programmed by injecting electrons from the cell channel into the nitride, where they are trapped and stored in a limited region. This stored charge then changes the threshold voltage of a portion of the channel of the cell in a manner that is detectable. The cell is erased by injecting hot holes into the nitride. See also Nozaki et al., “A 1-Mb EEPROM with MONOS. Memory Cell for Semiconductor Disk Application,”. IEEE Journal of Solid-State Circuits, Vol. 26, No. 4, April 1991, pp. 497-501, which describes a similar cell in a split-gate configuration where a doped polysilicon gate extends over a portion of the memory cell channel to form a separate select transistor.
Another approach to storing two bits in each cell utilizing a dielectric storage medium has been described by Eitan et al., “NROM: A Novel Localized Trapping, 2-Bit Nonvolatile. Memory. Cell,” IEEE Electron Device Letters, vol. 21, no. 11, November 2000, pp. 543-545. An ONO dielectric layer extends across the channel between source and drain diffusions. The charge for one data bit is localized in the dielectric layer adjacent to the drain, and the charge for the other data bit is localized in the dielectric layer adjacent to the source. Multi-state data storage is obtained by separately reading binary states of the spatially separated charge storage regions within the dielectric.
The use of dielectric charge storage media in NOR, NAND and other flash EEPROM architectures is further described in pending U.S. application Ser. No. 10/280,352, filed Oct. 25, 2002 by Harari et al., and entitled “Multi-State Non-Volatile Integrated Circuit Memory Systems that Employ Dielectric. Storage Elements”.
Interaction Between Neighboring Charge Storage Elements
As the number of states stored in each memory cell increases, the tolerance of any shifts in the programmed charge level on the storage elements decreases. Since the ranges of charge designated for each storage state must necessarily be made narrower and placed closer together as the number of states stored on each memory cell storage element increases, the programming must be performed with an increased degree of precision and the extent of any post-programming shifts in the stored charge levels that can be tolerated, either actual or apparent shifts, is reduced. Actual disturbs to the charge stored in one cell can be created when programming and reading that cell, and when reading, programming and erasing other cells that have some degree of electrical coupling with that cell, such as those in the same column or row, and those sharing a line or node.
In addition, apparent shifts in the stored charge levels occur because of field coupling between storage elements. The degree of this coupling necessarily increases as the spaces between memory cell storage elements are decreased, which is occurring as the result of improvements of integrated circuit manufacturing techniques. The problem occurs most pronouncedly between two groups of adjacent cells that have been programmed at different times. One group of cells is programmed to add a level of charge to their storage elements that corresponds to one set of data. After the second group of cells is programmed with a second set of data, the charge levels read from the storage elements of the first group of cells often appear to be different than programmed because of the effect of the charge on the second group of storage elements being capacitively coupled with that the first group. This is known as the “Yupin” effect, and is described in U.S. Pat. No. 5,867,429.
The effect of this parasitic capacitance between storage elements can be compensated by taking into account the effect of the charge on the second group of storage elements when reading that of the first group. Also, the effect may be reduced by physically isolating the two groups of storage elements from each other, such as by placing a conductive shield between the two groups. One way in which such shielding has been accomplished is to extend control gate lines, which run across either rows or columns of floating gates, downward between the floating gates. Further, it has been suggested that the parasitic capacitance between floating gates may be reduced by positioning a dielectric material between them, either in a solid or a non-solid form, which has a very low dielectric constant, but of course not less than 1.0. Another technique to reduce coupling between floating gates is to make them very thin so that their opposing surface areas are small.